-------------------working and simulated--------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_arith.all;
   use ieee.std_logic_unsigned.all;
--	USE work.LCSE.all;

	
	
entity RS232top is

  port (
    Reset     : in  std_logic;   -- Low_level-active asynchronous reset
    Clk       : in  std_logic;   -- System clock (20MHz), rising edge used
	 
    Data_in	  : in  std_logic_vector(7 downto 0);-- Data from dipswitches
    Valid_D   : in  std_logic;   -- Start_TX, TX button-- from spartan system, low when data is valid
    Ack_in    : out std_logic;   -- ACK for data received, low once data-- has been stored
    TX_RDY    : out std_logic;   -- System ready to transmit
    TD        : out std_logic;   -- from spartan system-- RS232 Transmission line
    RD        : in  std_logic;   -- from spartan system-- RS232 Reception line
    Data_out  : out std_logic_vector(7 downto 0);  --rx by spartan system--barleds, from tx rs232
    Data_read : in  std_logic;   -- 
	 Full      : out std_logic;   -- Full internal memory
    Empty     : out std_logic);  -- Empty internal memory

end RS232top;

architecture RTL of RS232top is
 
  ------------------------------------------------------------------------
  -- Components for Transmitter Block
  ------------------------------------------------------------------------

  component RS232_TX
    port (
      Clk   : in  std_logic;
      Reset : in  std_logic;
      Start : in  std_logic;--active high start tx
      Data  : in  std_logic_vector(7 downto 0);--bytes of data to tx
      EOT   : out std_logic;--end of tx
      TX    : out std_logic);--rs232 tx line
  end component;

  ------------------------------------------------------------------------
  -- Components for shift register
  ------------------------------------------------------------------------

  component ShiftRegister
    port (
      Reset  : in  std_logic;
      Clk    : in  std_logic;
      Enable : in  std_logic;--Permit to load and displacement active high and synchronous.
      D      : in  std_logic;--data arival
      Q      : out std_logic_vector(7 downto 0));--bytes rx by rs232-- Fifo_in
  end component;

   ------------------------------------------------------------------------
  -- Components for Receiver Block
  ------------------------------------------------------------------------
  component RS232_RX
    port (
      Clk       : in  std_logic;
      Reset     : in  std_logic;
      LineRD_in : in  std_logic;--rx rs232
      Valid_out : out std_logic;--Indicates data is valid and should be stored in the shift register, active high.
      Code_out  : out std_logic;--data output
      Store_out : out std_logic);--Indicates that the byte rx is valid & should be shifted from shift register memory,active high.
  end component;
 ------------------------------------------------------------------------
  -- Components for fifo
  ------------------------------------------------------------------------
  component fifo
    port (
      clk   : IN  std_logic;
      rst : IN  std_logic;
      din   : IN  std_logic_VECTOR(7 downto 0);--data write port
      wr_en : IN  std_logic;--active high
      rd_en : IN  std_logic;--active high
      dout  : OUT std_logic_VECTOR(7 downto 0);--data read port
      full  : OUT std_logic;--fifo full
      empty : OUT std_logic);--fifo empty
  end component;
 
  

  ------------------------------------------------------------------------
  -- Internal Signals
  ------------------------------------------------------------------------

  signal Data_FF    : std_logic_vector(7 downto 0);--bytes of data to tx from spartan to rx of rs232
  signal StartTX    : std_logic;  --tx from HW  spartan to rs232 rx
  signal TX_RDY_i   : std_logic;  --tx eot
   ---------------------------------------------------------------------------
  signal Fifo_write : std_logic;  --rx store_out
  signal LineRD_in  : std_logic;  -- internal RX line--rx
  signal Valid_out  : std_logic;  -- valid bit @ receiver--rx
  signal Code_out   : std_logic;  -- bit @ receiver output--rx
  ----------------------------------------------------------------------
  signal sinit      : std_logic;  -- fifo reset
  signal Fifo_in    : std_logic_vector(7 downto 0);--Q shift reg  
  

begin  -- RTL
---------------------------------
  Transmitter: RS232_TX
    port map (
					Clk   => Clk,
					Reset => Reset,
					Start => StartTX,
					Data  => Data_FF,
					EOT   => TX_RDY_i,
					TX    => TD);
------------------------------------
  Receiver: RS232_RX
    port map (
					Clk       => Clk,
					Reset     => Reset,
					LineRD_in => LineRD_in,
					Valid_out => Valid_out,
					Code_out  => Code_out,
					Store_out => Fifo_write);
--------------------------------------------
  Shift: ShiftRegister
    port map (
					Reset  => Reset,
					Clk    => Clk,
					Enable => Valid_Out,
					D      => Code_Out,
					Q      => Fifo_in);
----------------------------------------------
  sinit <= not reset;
  
  Internal_memory: fifo
    port map (
					clk   => clk,
					rst => sinit,
					din   => Fifo_in,
					wr_en => Fifo_write,
					rd_en => Data_read,
					dout  => Data_out,
					full  => Full,
					empty => Empty);
------------------------------------------------------------------

-- purpose: Clocking process for input protocol
  Clocking : process (Clk, Reset)
  begin
    if (Reset = '0') then  -- asynchronous reset (active low)
      Data_FF   <= (others => '0');
      LineRD_in <= '1';--active high
      Ack_in    <= '1';
    elsif (Clk' event and Clk = '1') then  -- rising edge clock
      LineRD_in <= RD;--RD from the HW
      
		if(Valid_D = '0' and TX_RDY_i = '1')then
        Data_FF <= Data_in;
        Ack_in  <= '0';
        StartTX <= '1';
      else
        Ack_in  <= '1';
        StartTX <= '0';
      end if;
    end if;
  end process Clocking;

  TX_RDY <= TX_RDY_i;

end RTL;


------------------------------------------------------------------------
  -- Component DMA
  ------------------------------------------------------------------------
-- component DMA
--  PORT (
--   Reset     : in  std_logic;--asynchronous reset
--   Clk       : in  std_logic;--20 MHZ
--   
--	----------------recieve data from rs232 to dma--------------------------------
--   RCVD_Data : in  std_logic_vector(7 downto 0);--
--										---RX_Full=0 then the fifo is not full it can rx data from the dma
--										---RX_Full=1 then the fifo is full and cant recieve more data
--	RX_Full   : in  std_logic;--status signal RX internal memory full--from rs232 to dma
--									--RX_Empty=0 fifo is full.then rs232 tx data to dma
--									--RX_Empty=1 fifo is empty.then rs232 waits to tx data to dma
--	RX_Empty  : in  std_logic;--status signal RX internal memory ---------from rs232 to dma
--	Data_Read : out  std_logic;--request to read data from the rs232
--   
--	--------------------transmit data from dma to rs 232------------------------------
--	TX_RDY    : in  std_logic;--state of machine serial tx
--	ACK_out   : in  std_logic;--ack for data rx from rs 232..data from rs232 to pc
--	Valid_D   : out  std_logic;--valid data sent to rs232TX
--   TX_Data   : out  std_logic_vector(7 downto 0);--send data to serial line
--   
--   -------------RAM------------------------------------------------------
--	CS        : out  std_logic;--chip select
--   Write_en  : out  std_logic;---write data to ram 
--   OE        : out  std_logic;--read  from ram
--   Address   : out  std_logic_vector(7 downto 0); --address bus
--	Databus   : inout  std_logic_vector(7 downto 0); --system data bus
--	
--	-----main control-----------------------------------------
--	DMA_ACK   : in  std_logic; --recognition and sharing of buses by the main processor
--   Send_comm : in  std_logic; --start of data tx
--	DMA_RQ    : out  std_logic; --request for bus to the processor
--   READY     : out  std_logic);  ---=1 when processor is idle, 0-> processor is busy 
--  
--  end component;
--  
--  ------------------------------------------------------------------------
--  -- Component RAM
--  ------------------------------------------------------------------------
--  component RAM
--  Port(
--			Reset : in std_logic;
--			Clk : in std_logic;								
--			Databus : inout std_logic_vector( 7 downto 0); ---data bus
--			Address : in std_logic_vector(7 downto 0);  --address bus
--			CS : in std_logic;			--chip select
--			write_en : in std_logic;   --write enable
--			OE : in std_logic;			--read enable
--			Switches : out std_logic_vector(7 downto 0); ---switch state
--			Temp_L : out std_logic_vector(6 downto 0);		---7 segment display lowest temperature value of thermostat
--			Temp_H : out std_logic_vector(6 downto 0));		---7 segment display highest temperature value of thermostat
--		end component;
--  
--   ------------------------------------------------------------------------
--  -- Component ALU
--  ------------------------------------------------------------------------
--  
--  component ALU
--	port(
--			Reset : in std_logic;
--			Clk : in std_logic;
--			u_instruction : in alu_op;-- U-instruction from the cpu
--			FlagC : out std_logic;--carry flag
--			FlagZ : out std_logic;--Zero flag
--			FlagN : out std_logic;--carry bit Nibble flag
--			FlagE : out std_logic;--error flag
--			Index_Reg: out std_logic_vector(7 downto 0);--index register
--			Databus: inout std_logic_vector(7 downto 0));
--		end component;
--	



--full_ram: RAM
--	port map(
--			Reset=>Reset, 
--			Clk =>Clk,								
--			Databus=>Databus,  ---data bus
--			Address =>Address,  --address bus
--			CS =>CS,			--chip select
--			write_en=>write_en,    --write enable
--			OE 	=>OE,		--read enable
--			Switches=>Switches,  ---switch state
--			Temp_L 	=>	Temp_L, ---7 segment display lowest temperature value of thermostat
--			Temp_H => Temp_H);	
-------------------------------------------------------------------------
--dma_controller:DMA
--	port map(
--				Reset=>Reset,           
--				Clk   =>Clk,
--				RCVD_Data=>RCVD_Data, 
--				RX_Full   =>RX_Full,
--				RX_Empty  =>RX_Empty,
--				Data_Read =>Data_Read,
--				TX_RDY    =>TX_RDY,
--				ACK_out   =>ACK_out,
--				Valid_D   =>Valid_D,
--				TX_Data   =>TX_Data,
--				CS        =>CS,
--				Write_en   =>Write_en,
--				OE        =>OE ,
--				Address   =>Address,
--				Databus   =>Databus,
--				DMA_ACK   =>DMA_ACK,
--				Send_comm =>Send_comm,
--				DMA_RQ    =>DMA_RQ,
--				READY      =>READY);
----------------------------------------------------------------------------------------
--arith: ALU
--port map(
--			Reset=> Reset,           
--			Clk => Clk,
--			u_instruction=> u_instruction, -- U-instruction from the cpu
--			FlagC=> FlagC,--carry flag
--			FlagZ=> FlagZ,--Zero flag
--			FlagN=> FlagN,--carry bit Nibble flag
--			FlagE=> FlagE,--error flag
--			Index_Reg=> Index_Reg,--index register
--			Databus=> Databus);
-------------------------------------------------------------------------------------